EnCore Microprocessor

Ini dia sebuah temuan terbaru di dunia teknologi informasi oleh para ilmuan dari University of Edinburgh, Skotlandia, yaitu sebuah microprocessor jenis baru yang diberi nama EnCore. Mikroprosesor ini mampu meningkatkan kemampuan MP3 Player dan ponsel 4G menjadi lebih hemat daya. EnCore pun memberikan kemampuan proses yang lebih cepat, namun demikian power dan ruang penyimpanannya lebih sedikit dibanding perangkat sejenis lainnya yang telah beredar di pasaran.
Salah satu pengembang Encore tersebut, Prof. Nigel Topham dari School of Informatics, University of Edinburgh mengatakan, "Jika perangkat ini digunakan pada ponsel, maka akan melonggarkan daya tahan baterai, meskipun belum diketahui berapa lama dapat bertahan. Prosesor ini mengusung konsumsi daya yang rendah dibanding prosesor komersial lainnya, pengguna pun dapat melakukan kostumisasi prosesor dan menambah aplikasi yang dapat dijalankan."
Beliau pun menyatakan bahwa pihaknya merasa bangga karena chip temuannya dapat bekerja dengan stabil meskipun dengan konsumsi rendah daya.

Sebenarnya mikroprosesor EnCore ini telah dikembangkan selama 4 tahun sebagai bagian dari proyek yang disponsori oleh Engineering and Physical Science Research Council (EPSRC). Yang bertujuan untuk meneliti metode baru pengembangan device komputer.
Berikut penjelasan lengkap tentang Encore Microprocessor dari School of Informatics, University of Edinburgh.

The EnCore microprocessor family is a configurable and extendable implementation of the ARCompact® instruction-set architecture. It is designed to fulfill the following aims and objectives:
  • Low-complexity and low gate-count design.
  • Highest operating frequency in its class.
  • Lowest possible dynamic energy consumption. EnCore has a target of 99% of flip-flops automatically clock-gated using typical Cadence and Synopsys synthesis tools.
  • Best-in-class CPI (cycles-per-instruction), with most non-memory operations achieving single-cycle latency, and no more than one load-delay slot.
  • Minimized branch penalties, resulting in an overall Dhrystone performance of at least 1.4 DMIPS / MHz.
  • Easy configurability of cache architectures and support for either 16 or 32 GPRs. These features have the most significant impact on both performance and die area for processors in this class.
  • Clean design, easily maintained and extended.
These design objectives are addressed through the use of a relatively short pipeline, comprising four main stages plus a fifth stage devoted solely to the write-back of results. The design supports separate instruction and data caches, each of which can be configured in terms of size, associativity and block size.
The design of any processor involves trade-offs between logical complexity and CPI, as each CPI-improving technique requires the investment of additional logic. There is also a trade-off between CPI and operating frequency, as CPI improvements often lengthen critical paths. EnCore achieves a comparatively high operating frequency of around 375 MHz in a standard TSMC 0.13 ┬Ám G process. This requires streamlined control logic particularly in areas such as instruction alignment, zero-overhead loop management, and the handling of complex but infrequent data cache events. It also relies, where possible, on the sharing of data-path elements for multiple purposes. This helps to minimize logical complexity, and yields gate counts as low as 20-24 kgates for a typically configured core. (dari berbagai sumber)

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